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Test Paper :1
Posted By : admin

Cosco Text patten consist of

1. Written Test
2. Technical Interview
3. HR Interview

Written text consist of
1.Aptitude- 20Q
2.C - 30Q
3.Networking - 20Q
4.JAVA - 20Q (optional)

5.OS - 20Q
Here Java section is optional,To clear the written test just be thorough with C. Concentrate more on Pointers. Sorry, I could not remember the questions other than these,

Interview Procedure :
The written test is followed by a lengthy technical interview. The interview may last up to 1 hour or more. It is entirely technical with questions on all basic fundamentals.

Test Paper :2
Paper Type : Candidate Experiences
Test Date : 17 August 2006
Test Location : CUSAT, COCHI
Posted By : Sanjay Kumar

CISCO PAPER PATTERN ON 17th AUGUST 2006 AT COCHI

Hi friends, cisco visit my campus(CUSAT,cochin) on 17-08-06.cisco selected 4 students out of 24 who selected out of 500 after written exam.
I didn't get selected.cutoff was high.(44/50).so u should score high to clear the test.i don't more about technical question,but according to my friend who selected,u must have a sound knowledge of basics.because they search for best talent..so be confident abt your fundamentals.u can get...
Pattern:
test was conducted by cisco.time allocated was one hour & total no. of questios were 50.there was no negative marking.
papers contains aptitude,digital electronic,microprocessor,c(pointer),os,data structure,networking.
questions were not so easy.aptitude was relatively easier sections among those.tech were tougher.
exa:aptitude sections consists of probality,ven diagram,relative velocity(train),men & work,series sum,etc..
os-semaphore
ds-binary tree,stack...
mp-memory based i/o,...
de-simplification(AB+BC+AC).,flip flop,.
electonics-diode,rectifier,

By, Sanjay Kumar.

Test Paper :3
Paper Type : Aptitude - General
Posted By : admin



SECTION 1 -- BASIC DIGITAL SECTION



1.

In order to find out stack fault of a three input nand gate how many necessary input vectors are needed ?
2.

What is parity generation ?
3.

A nand gate becomes ___ gate when used with negative logic ?
4.

What is the advantage of cmos over nmos ?
5.

What is the advantage of synchronous circuits over asynchronous circuits ?
6.

What is the function of ALE in 8085 ?
7.

A voice signal sample is stored as one byte. Frequency range is 16 Hz to 20 Hz. What is the memory size required to store 4 minutes voice signal?
8.

What will the controller do before interrupting CPU?
9.

In a normalized floating point representation, mantissa is represented using 24 bits and exponent with 8 bits using signed representation. What is range ?
10.

The stack uses which policy out of the following-- LIFO, FIFO, Round Robin or none of these ?
11.

Where will be the actual address of the subroutine is placed for vectored interrupts?
12.

Give the equivalent Gray code representation of AC2H.
13.

What is the memory space required if two unsigned 8 bit numbers are multiplied ?
14.

The vector address of RST 7.5 in 8085 processor is _______.
Ans. 003C (multiply 7.5 by 8 and convert to hex)
15.

Subtract the following hexadecimal numbers--- 8416 - 2A16
16.

Add the following BCD numbers--- 1001 and 0100
17.

How much time does a serial link of 64 Kbps take to transmit a picture with 540 pixels
18.

Give the output when the input of a D-flip flop is tied to the output through the XOR gate.
19.

How much time does a serial link of 64 Kbps take to transmit a picture with 540 pixels.
20.

Give the output when the input of a D-flip flop is tied to the output through the XOR gate

Implement the NOR gate as an inverter.
21.

What is the effect of temperature on the Icb in a transistor
22.

What is the bit storage capacity of a ROM with a 512*4 organization?
23.

What is the reason of the refresh operation in dynamic RAM's ?
24.

Suppose that the D input of a flip flop changes from low to high in the middle of a clock pulse. Describe what happens if the flip flop is a positive edge triggered type?
25.

How many flip flops are required to produce a divide by 32 device ?
26.

An active HIGH input S-R latch has a 1 on the S input and a 0 on the R input. What state is the latch in?
27.

Implement the logic equation Y = C^BA^ + CB^A + CBA with a multiplexer.
(where C^ stands for C complement)
28.

Equivalent Gray code representation of AC2H.
29.

What does a PLL consist of ?

II - Software Section

1.

The starting location of an array is 1000. If the array[1..5/...4] is stored in row major order, what is the location of element [4,3]. Each word occupies 4 bytes
2.

In a tertiary tree, which has three childs for every node, if the number of internal nodes are N, then the total number of leaf nodes are
3.

Explain the term "locality of reference" ?
4.

What is the language used for Artificial Intelligence
Ans: lisp
5.

What is the character set used in JAVA 2.0 ?
Ans: Unicode
6.

char a =0xAA ;
int b ;
b = (int) a ;
b = b >> 4 ;
printf("%x",b);
What is the output of the above program segment ?
7.

struct s1 { struct { struct { int x; } s2 } s3 }y; How does one access x in the above given structure definition ?
8.

Why there is no recursion in Fortran ?
Ans. There is no dynamic allocation.
9.

What is the worst case complexity of Quick sort?
Ans. O(n2)
10.

What will be sequence of operating system activities when an interrupt occurs ?

Test Paper :4
Paper Type : Aptitude - General
Posted By : admin



Some Sample questions (m.tech.) tech.--24, apti.--20

1.

On cmos power( formula- P=CV*Vf
2.

Lowest noise margin in which logic family--
a) TTL b) CMOS c) biCMOS d) all have same
3.

If CMOS has tr(rise time)=tf.find Wp/Wn. given beta(n)=2*beta(p)
4.

gm of a transistor is proportional to
a)Ic b)Vt c)1/Vt d)none
5.

If A and B are given in 2's complement find A-B in decimal.
6.

Set up time,hold time ,clock to Q delay time (very important)
7.

.3 questions on opamp (transfer function)(2 marks each)
8.

2 questions on sequence detector (2 marks each)
9.

Logic function boolean expressions(true/false) (3 question-1 mark each)probabily all false
10.

In I/O mapped how do you represent memory(1 mark)
11.

The design of FSM(finite state machine) will--
a) increase time of design
b) increase delay
c) increase power
d) all of the above
12.

K-map minimization
13.

Phase locked loop(PLL) 1 question sachin